1. Field of the Invention
The present invention relates to a semi-fixed circuit, and particularly relates to a semi-fixed circuit capable of a plurality of kinds of circuit operations.
2. Description of the Related Art
As data processing required in many communication standards, for example, the mobile communication standard W-CDMA, and wireless LAN standards IEEE802.11a and IEEE802.11b, a quasi-random code generator by a scrambler, a convolution coder (convolution encoder), an error detecting type CRC (Cyclic Redundancy check) circuit, and a linear feedback shift register is conventionally used. Fast Fourier transform (FFT) constituted of a Viterbi decoder, a matched filter, and butterfly computation executing complex multiplication and complex addition is used.
In the following Patent Documents 1 and 2, a pseudo-random number generating circuit using a linear feedback shift register is described. In the following Patent Document 3, a variable CRC generating circuit is described.
[Patent Document 1] Japanese Patent Application Laid-open No. 63-67628.
[Patent Document 2] Japanese Patent Application Laid-open No. 63-204919.
[Patent Document 3] Japanese Patent Application Laid-open No. 4-292018.
A scrambler, a convolution encoder and the like are constituted of separate fixed circuits, since their processing contents differ. Even the same scramblers are constituted of separate fixed circuits when they are the scramblers with different standards. It reduces the efficiency of using hardware resources to construct all of them by separate fixed circuits.